Shallow trench isolation (STI) structures are commonly used to isolate active regions of semiconductor devices. FIGS. 1-3 illustrates an existing fabrication process of a STI structure.
As shown in FIG. 1, the process includes providing a substrate 100; and forming a trench 101 in the substrate 100. Further, as shown in FIG. 2, the process includes forming an isolation film 102 on surface of the substrate 100; and fills the trench 101. Further, as shown in FIG. 3, the process also includes polishing the isolation film 102 until the surface of the substrate 100 is exposed. Thus, a STI structure 103 is formed in the trench 101.
With the continuous development of semiconductor technology, the critical dimension (CD) of the semiconductor devices has become smaller and smaller; and the integration level of the semiconductor devices have been consciously increased. Thus, the size of STI structures is correspondingly reduced. The size reduction of the STI structures has cause the height-to-width aspect ratio of the STI structure to be continuously increased; and it is easy to form voids inside the isolation film 102 formed in the trench 101. The voids may significantly affect the isolation properties of the isolation structure 103.
In order to improve the quality of the isolation layer 102, a high aspect ratio process (HARP) is used to form the isolation layer 102. The isolation layer 102 formed by the HARP is able to match the requirement for a high respect ratio. Further, the voids in the isolation layer 102 formed by the HARP may be reduced, or avoided.
However, such STI structures formed by the HARP may have certain detrimental effects to the semiconductor devices subsequently formed on, and/or in the substrate 100. Thus, the performance of the semiconductor devices may be reduced. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.